1. Field of the Invention
This invention relates, in general, to semiconductor manufacturing, and more particularly the invention typically relates to multi-damascene structures and methods for their fabrication.
2. Description of the Related Art
One of the primary challenges in the production of semiconductor devices involves the ability to create circuits of increasing density with smaller and smaller critical dimensions. As devices become smaller and have higher resolution, production costs become a greater concern, especially at the sub-micron level and smaller.
One type of conventional semiconductor manufacturing method is the damascene process. The damascene semiconductor processing method differs from conventional semiconductor processing methods in that the metal lines are not etched. Rather, the metal conductor is deposited in grooves formed within a dielectric layer. Excess metal is then removed by chemical mechanical polish (CMP) techniques and other techniques. In general, a single damascene process involves lithographic patterning, trench or hole imaging, gap filling with conductor, and then CMP. A dual damascene process typically involves repeating the damascene structure for one layer having a hole and another layer having a trench, and then simultaneously filling both the trench and the hole with metal.
The damascene process and the dual damascene process are popular for laying metal lines and interconnects on chips. An advantage of the damascene process is that the many of the processing problems associated with metal etch steps, including corrosion, resist burn, and time critical with resist are reduced. This is due in part to the use of lithographic patterning. Lithography processes, however, typically drive up the overall cost of the production process significantly.
Semiconductor manufacturing techniques typically involve several costly lithography steps. Conventional industry approaches utilize more than one ILD layer or etch stop to pattern the insulative layer. These approaches employ two separate lithographic and RIE steps to create a dual damascene cavity profile. Additional lithographic and material removal processes are required for each additional layer. The production complexity also increases exponentially with additional layers.
The lithographic imaging step is one of the most expensive steps in the device fabrication process. Also, the two RIE material removal steps add additional cost and complexity to dual damascene process.
Accordingly, there is a need for a method to create a multi-layer damascene pattern on a substrate with reduced complexity and costs. What is needed is a device and methods which overcome the above and other disadvantages.